A VLSI Architecture for Concurrent Data Structures

Concurrent data structures simplify the development of concurrent programs by encapsulating commonly used mechanisms for synchronization and communication into data structures. This thesis develops a notation for describing concurrent data structures, presents examples of concurrent data structures, and describes an architecture to support concurrent data structures. Concurrent Smalltalk (CST), a derivative of Smalltalk-80 with extensions for concurrency, is developed to describe concurrent data structures. CST allows the programmer to specify objects that are distributed over the nodes of a concurrent computer. These distributed objects have many constituent objects and thus can process many messages simultaneously. They are the foundation upon which concurrent data structures are built. The balanced cube is a concurrent data structure for ordered sets. The set is distributed by a balanced recursive partition that maps to the subcubes of a binary n-cube using a Gray code. A search algorithm, VW search, based on the distance properties of the Gray code, searches a balanced cube in O(log N) time. Because it does not have the root bottleneck that limits all tree-based data structures to O(1) concurrency, the balanced cube achieves O(~og ) concurrency. Considering graphs as concurrent data structures, graph algorithms are presented for the shortest path problem, the mix-flow problem, and graph partitioning. These algorithms introduce new synchronization techniques to achieve better performance than existing algorithms. A message-passing, concurrent architecture is developed that exploits the characteristics of VLSI technology to support concurrent data structures. Interconnection topologies are compared on the basis of dimension. It is shown that minimum latency is achieved with a very low dimensional network. A deadlock-free routing strategy is developed for this class of networks, and a prototype VLSI chip implementing this strategy is described. A message-driven processor complements the network by responding to messages with a very low latency. The processor directly executes messages, eliminating a level of interpretation. To take advantage of the performance offered by specialization while at the same time retaining flexibility, processing elements can be specialized to operate on a single class of objects. These object experts accelerate the performance of all applications using this class

Deadlock Free Message Routing in Multiprocessor Interconnection Networks

A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels. A necessary and sufficient condition for deadlockfree routing is the absence of cycles in the channel dependency graph. Given an arbitrary network and a routing function, the cycles of the channel dependency graph can be removed by splitting physical channels into groups of virtual channels. This method is used to develop deadlock-free routing algorithms for k-ary n-cubes, for cube connected cycles, and for shuffleexchange networks

Transmitter Equalization for 4Gb/s Signalling

To operate a serial channel over copper wires at 4Gb/s, we incorporate an 4GHz FIR equalizing filter into a differential transmitter. The equalizer cancels the frequency-dependent attenuation caused by the skin-effect resistance of copper wire giving a frequency response that is flat to within 5% over the band from 200MHz to 2GHz even over wires with 6dB of high-frequency attenuation. All but the last stage of the transmitter operates at 400MHz. The transmitter output stage uses a stable 10-phase 400MHz clock to sequence an array of drivers that implement the FIR filter. This paper introduces the concept of digital-signal equalization, describes the system design and circuit design of our equalizing transmitter, and presents simulation results from a 4Gb/s 0.5µm CMOS transmitter. 1. Introduction The performance of many digital systems is limited by the interconnection bandwidth between chips, boards, and cabinets. As VLSI technology continues to scale, system bandwidth will become an ..

Some considerations on coastal processes relevant to sea level rise

The effects of potential sea level rise on the shoreline and shore environment have been briefly examined by considering the interactions between sea level rise and relevant coastal processes. These interactions have been reviewed beginning with a discussion of the need to reanalyze previous estimates of eustatic sea level rise and compaction effects in water level measurement. This is followed by considerations on sea level effects on coastal and estuarine tidal ranges, storm surge and water level response, and interaction with natural and constructed shoreline features. The desirability to reevaluate the well known Bruun Rule for estimating shoreline recession has been noted. The mechanics of ground and surface water intrusion with reference to sea level rise are then reviewed. This is followed by sedimentary processes in the estuaries including wetland response. Finally comments are included on some probable effects of sea level rise on coastal ecosystems. These interactions are complex and lead to shoreline evolution (under a sea level rise) which is highly site-specific. Models which determine shoreline change on the basis of inundation of terrestrial topography without considering relevant coastal processes are likely to lead to erroneous shoreline scenarios, particularly where the shoreline is composed of erodible sedimentary material. With some exceptions, present day knowledge of shoreline response to hydrodynamic forcing is inadequate for long-term quantitative predictions. A series of interrelated basic and applied research issues must be addressed in the coming decades to determine shoreline response to sea level change with an acceptable degree of confidence. (PDF contains 189 pages.

The MOSSIM Simulation Engine Architecture and Design

As the complexity of VLSI circuits approaches 10 to the power of 6 devices, the computational requirements of design verification are exceeding the capacity of general purpose computers. To provide the computing power required to verify these complex VLSI chips, special purpose hardware for performing simulation is required. Existing simulation engines which perform logic simulation are inadequate for MOS VLSI because they cannot accurately model MOS circuits. Switch-level simulation, on the other hand, models the affects of capacitance and transistor ratios at speeds comparable to logic simulation. The MOSSDM Simulation Engine (MSE) is a special purpose processor for performing switch-level simulation of MOS VLSI circuits. A single processor MSE perfonns switch=level simulation 200 to 500 times faster than a VAX 11/780. Several MSE processors can be connected in pallel to achieve additional speedup. A virtual processor mechanism allows the MSE to simulate large circuits with the size of the circuit limited only by the amount of backing store available t o hold the circuit description. Functional simulation is provided on the MSE to facilitate the efficient simulation of large circuits